Memory devices are used to store data in digital electronic devices such as computers. The demand for large memory systems with high bandwidth and low power consumption has increased during recent years. Early multi die memory devices in digital electronics included a plurality of dies connected in parallel to a common bus such a system is said to be connected by a multi-drop bus. Multi-drop connection with several memory device dies connected to a common bus in parallel is commonly used for a large memory system.
Flash memory system with daisy chain connection have a serial connected clocking system to mitigate loading effect from the parasitic resistive and capacitive loading of PCB and multi-drop connection inducing heavy input capacitance issues. When clock is bypassed through devices on the series connected ring system, clock's shape is distorted and duty cycle is not kept as original input clock.
FIG. 1 Shows a typical series connected clocking system. Each device obtains a clock signal CK and CK# from the next upstream device except for the first device (0) which obtains the clock signal from an external clock. This system can easily generate distortion which increases for each downstream device.
In order to compensate this distortion of clock shape which is even more important in DDR (Dual Data Rate) devices which operate with a 50:50 duty cycle, a PLL (Phase-Locked-Loop) has to be incorporated into each device. By this PLL, each every device on the series connected device generates duty corrected clock to next device as shown in FIG. 2.
FIG. 3 Shows PLL locking time for each device on the daisy chained memory system and illustrates the problem of consecutive PLL locking control Once PLL is locked, a locking flag signal is generated from the PLL and system can recognize PLL locking status. However, in case of daisy chained memory system, each every device has PLL so PLL locking time could be different among them and system does need to choose which PLL locking information has to be taken from them.
Depending on PLL design type (digital PLL or analog PLL), its locking time is varied along with PVT change at each device. Therefore, the anticipation that the last device on the daisy chained memory system would have longest PLL locking time among them is incorrect.
FIG. 3 illustrates the problem with PLL locking time sequence in a daisy chained memory system. It is apparent that each module has a random lock time. This unexpected sequence of PLL locking time is caused by phase difference from PLL reference clock of each device and source clock from the controller. Only the PLL locking time of the first device on the daisy chained memory system is the fastest among all devices on the same ring, others do not have any determined sequences. Without monitoring PLL locking status of all devices, the controller is unable to transfer any specific command and data securely. The unstable clock threatens malfunction of individual device operations. In addition the timing does not ensure correct phase relationships of block to block into each every device the result could invoke data loss and data contention.